Syllabus EET 207

Oregon Institute of Technology (Portland)

Electronics Engineering Technology Department

Course Title EET 207 – Topics in Digital Circuits

CRN 42105

Substitute for CST 312 and EET 283

Credit Hours 4

Monday/Wednesday 6-10pm at CAPITAL center  (Use Entrance A, security people can direct you to the room)

    Additional contact time to be discussed at the first lab if needed
    email for questions : steen.larsen AT

Instructor :  Steen Larsen    : Sr Design Engineer, Intel Corp.

Prerequisites :  Basic Course in Digital Circuits:

EET 283 is a "Bridge Course". It is intended to allow you to cross from your background to OIT upper division classes. In particular EET 207 will prepare you for EET 313.

Text and Special Materials

  1. Roth, C H., Jr., Fundamentals of Logic Design, West, 5th ed.  ISBN 0-534-27804-8
  2. Lab material (in the form of breadboards, chips, PLD development boards) will be provided but tools such as oscilloscopes and DMMs will need to remain in the lab.


Total 100 points


Midterm/Final will be based on questions from homework and lab environment.  The text and lecture slides cover much more material but if you focus on what the homework and lab is trying to describe you will do well and at least get a a B grade.  Dates for midterm/final will be discussed in the first couple weeks of lab and then communicated online.

Name tents should be displayed in labs for the first few sessions to help the Steen remember names.

Between classes, to ask a question, or get in touch with the instructor, the preferred method is via e-mail. During normal working hours, the instructor checks e-mail  on steen.larsen AT  If the instructor deems a question of general interest, the answer will be e-mailed to the entire class. If the need is urgent, the instructor can be contacted at:

Steen Larsen    Work: (503) 712-4452

Main Lab format:

  1. Lab 1 : TTL Parameters Familiarize with gate logic and lab equipment
  2. Lab 2 : Combinational and State Logic Build logic and simple state machines
  3. Lab 3 : Replicate lab 2 in Altera CPLD and show proper simulations to validate function
  4. Lab 4 : Personal project on Altera CPLD

Lab reports are due at the end of class on due date.  Assignments will be accepted without penalty until 12:00 Noon the next day.  Late grades will be deducted 10% of possible grade, and labs handed in after subsequent class period will not get credit.


Lab Number

Name Write-up Due Date
1 TTL Parameters Week 4 : July 19
2 Combinational/Sequential Logic Week 5 : July 26
3 Repeat Lab 2 in CPLD Week 6 : August 2
4 Personal Project Week 7 : August 9

If you cannot make the scheduled lab times, you can as security people to open the lab door for you.  They are available 7am-10pm weekdays and 7am-6pm Saturday.  Other than a class Wednesday evening there should be no conflict.

Writing skills are very important. Most job position listing in High Tech include a statement such as: "excellent written and oral communication skills". Lab reports need to do more than report what data was taken. Lab reports should include the following:

Set the stage. Get the reader to know what you are doing, and why. The reader needs to quickly be able to determine if they want to spend the time to read your report. Everyone in a work environment has lots of things going on at once. Even if your report is the hottest item in the office, don’t assume everyone who picks up your report knows what it is about.

Tell how you are getting your results. What equipment is being used (be specific, brand, model, serial number, etc.), and what are the limitations. For example when using an oscilloscope, you don’t need to give all of the specifications, but list its bandwidth. List assumptions that are being made.

Show all of the data, and all of the calculations being made with the data. If a lot of data is being taken and analyzed, show the analysis, then show the data in tabular form. If graphs or other visual presentations of the data will help your reader understand your analysis, show them. State analyses that are the result of a single test, or the result of tests taken together.

Tell the reader what they should take away from the report. Is there something central that was learned. Should a decision be made from the procedure and analysis you did. Make what you did valuable, even if the value is only in discarding a path to pursue (a very valuable result!)

Outline of instruction

If you are not available to hand in homework, you can email or fax to the CAPITAL center on the due date (before midnight).  Please call the OIT desk at 503-725-2133 for the fax number.  Please remember to show your work and thinking where applicable for partial credit.

Due Date

Text units





1.1c,d 1.2 1.10,2.2,2.4,2.10,2.13

Number systems and Boolean algebra



3.6a or 3.6b solved any method you choose

Boolean algebra and simplification



6.10 6.16 6.19

Applications of Boolean algebra




Quine-McCluskey Method



4.1 4.6 4.7 5.6 5.22 5.25

Karnaugh maps



7.2 8.1 9.15

Multilevel gates, muxes, decoders, ROMS, PLAs Combinatorial design and flip-flops



10.2 10.9 10.14 11.2

VHDL and flip-flops



12.9, 13.11

Registers, counters and sequential circuits




Derivation of state graphs  (Midterm in class)




Reduction of state tables and state assignments  and sequential network design



 15.20 (using D-FF only and optional)

Arithmetic operations




PLD design and VHDL



20.3 (20.6 is extra credit)

comprehensive review for final (last HW due and Lab4 due)




Final exam in class